1. Field of the Invention
The invention relates to the servicing of interrupts and, in particular to the servicing of interrupts in connection with nested subroutines.
2. Description of Related Art
In processing systems, it is common to utilize interrupt servicing subroutines to facilitate the processing of multiple demands for shared resources, e.g. memories. These subroutines typically include instructions for disabling further interrupts, until completion of the current interrupt, and then re-enabling interrupts. The primary purpose of this disable/enable feature is to ensure that conflicting demands for the same resources are serviced without corrupting already-existing information.
In some situations, the simple acts of disabling and then re-enabling interrupts in beginning and end portions, respectively, of each interrupt subroutine are inadequate to prevent the corruption of information. For example, it is sometimes desirable to permit nesting of a second subroutine within a first, each of which includes its own disable and enable interrupt instructions. The end of the nested second subroutine can include an enable interrupt instruction followed by a return instruction to effect return to and completion of the first subroutine. However, if a request for servicing another interrupt is pending when the nested second subroutine issues its enable interrupt instruction, the other interrupt could be serviced by a third subroutine before completion of the first. If the third subroutine is sharing memory locations still being used by the first subroutine, the third subroutine could modify and inadvertently corrupt information in these shared memory locations. Alternatively, these memory locations could contain incorrect information, e.g. memory addresses which had not yet been updated by the first subroutine. In this case the third subroutine could either read or store information at an incorrect address.
A known solution to this problem is to first store pertinent data (e.g. a processor status word) relating to the status of a processor performing the nested subroutines, disable interrupts to facilitate performance of one of the subroutines, and then to read the stored data and restoring the processor to its earlier status before reenabling interrupts. This solution is both time and memory consuming.
European Patent 441054 discusses this problem generally and proposes as a solution a combination of register banks, status bits and interrupt logic for servicing interrupts. It is desirable to provide a simpler solution.
It is an object of the invention to provide a simple method for servicing interrupts that effectively avoids the problem of corrupting information stored in memory.
Note that the word xe2x80x9cmemoryxe2x80x9d, as used herein, is intended to be interpreted as generally as is consistent with the manner in which it is used and includes, without limitation, volatile and non-volatile devices of various types, such as registers, RAMs, DRAMs, ROMs, LiFOs, FlFOs, etc.
In accordance with the invention, in the operation of a processor having the capability of performing nested subroutines in response to requested interrupts, a method of servicing such interrupts includes:
providing an indicator representing a current interrupt enable status;
saving status data including the indicator;
placing the current interrupt enable status in a disabled state;
at least beginning performance of an action designated by the requested interrupt;
before accepting another interrupt request:
reading the indicator from the saved status data;
placing the current interrupt enable status in the state indicated by the indicator.